Priorities for gallium nitride over the next decade

For any semiconductor, packaging is important for electrical isolation, product robustness, and thermal management.This is especially important for power semiconductors.With the shift to wide-band gap (WBG) materials such as silicon carbide (SiC) and gallium nitride (GaN), the higher current densities and switching speeds achieved by these materials have brought more stringent packaging requirements.When dealing with GaN, there are two additional considerations to optimize device performance compared to silicon (Si).The fast switching potential of GaN is realized through two-dimensional electron gas (2DEG) channel at GaN/AlGaN heterojunction interface.GaN has poor thermal conductivity.(About 1.3 W/ cm.k at 300 K, compared with 1.49 W/ cm.k for silicon and 3.7 W/ cm.k for silicon carbide) Assume that the thermal conductivity of the body is not significantly lower than that of silicon, but keep in mind the higher current density — it is limited to a small region around the heterojunction.Although not ideal, traditional Si packages can and have been used to package WBG devices such as GaN.To-247 packages are commonly used in silicon (Si) power MOSFEts and IGBTs where the die bottom (i.e., drain or collector contacts) engages directly TO the copper lead frame.When used in applications, it is standard practice to mount it directly to the radiator using a through-hole opening.This idea was fairly well transferred to SiC MOSFets, which have similar structures to their Si counterparts.Today, however, GaN devices have a horizontal design that is limited to the top of the chip.This means that most of the cooling benefits are lost.Another challenge posed by horizontal GaN structures is layout dependency.All three device terminals (gate, source, and drain) require pads and associated bonding wires to be installed around the chip in some way.One of the main selling points of using GaN is the ability to reduce product size.Therefore, for Si power FETs in discrete TO-247 packages, the same voltage and current rated GaN counterparts can be packaged in surface-mount QFN type packages.Unfortunately, this makes things more challenging from a thermal management perspective.Keep in mind that higher current densities will require more stringent packaging solutions — the smaller chips in QFN require more thermal management, not less.Today, some manufacturers have begun to adapt these packages to suit their applications.For example, see Navitas NV6128, a monolithic integrated GaN IC that fits multiple output ports in a QFN package.As shown in the figure below, you can see the bottom of the package with port annotations.The GaN Die is located on one side of the top of the cooling pad “CP”.That was clearly enough for the device;Interestingly, though, for Navitas’ recently announced 3rd generation gans with “GaN Sense”, they are focusing on control circuits for detecting and controlling operating temperatures.Other manufacturers have begun to look at GAN-specific packaging solutions.GaN Systems, for example, has several packages in which chips are embedded.A cross section of GS61008P is shown below.The copper columns are connected directly to the top and bottom of the core through the package holes, and then they are connected to the radiator.What is another consideration for GaN – optimizing switching performance?Minimization of encapsulated parasitic components is the key to achieve this goal.EPC takes the radical approach of essentially packageless or “wafer level” packaging.This is essentially just a passivated chip with a solder bump/electrode for direct connection to a PC (see figure below).Due to the lack of an associated bonding line, the parasitic inductance is minimized, as is the thermal resistance source of the interface, since the chip itself can theoretically bond directly to the radiator.However, circuit designers need to pay attention to and possibly special conditions during chip mounting.EPC recently broke with this tradition by introducing a package called the EPC2302.This top-exposed situation seems to be a compromise between wafer size and embedded chips.Another way to reduce inductance comes from Nexperia’s “copper clip” design.Again, the idea is to minimize parasitic inductance by removing the bonding lines.A cross section of a PSMN3R9 Si MOSFET is shown below (note that this package has also been applied to GaN devices).The image below shows the plan of the device, which has been jet-etched to expose the copper clamp.This welds directly to the source contact of the chip.Summary Although the custom packaging of GaN and other wideband gap devices is still in its infancy, it is a topic that will be greatly developed in the next decade.Innovative solutions to transfer device terminals such as underpad circuit (CUP) structures and through-GAN grooves are beginning to enter the market.Academic research is currently underway on better thermal interface materials and chip bonding methods.A shift from traditional welding to sintering using silver is gaining momentum.GaN has yet to find a foothold in high-power module design, but in cutting-edge SiC modules we are starting to see special ceramic substrates (such as Si 3 N 4 and AlN) for excellent heat dissipation.Does Die itself have a solution?Power Integrations has taken the approach of using gallium nitride wafers on sapphire substrates rather than silicon substrates, while academic research has looked at more exotic methods, such as GaN grown on diamond.Like all power semiconductors, there is no one-size-fits-all approach, and I think we will see more diversity and tailored solutions moving forward, which will be fascinating!

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